The invention relates to a circuit arrangement for the testing circuit components which are formed as integrated circuits.
A circuit arrangement of this kind is described in "In-Situ Testability Design" by Frank F. Tsui Proceedings of the IEEE, Volume 70, No. 1, January 1982, pages 59 to 78. In this known circuit arrangement, a base plate (wafer) on which a plurality of integrated circuit components (chips) are formed is provided with many external connecting areas (pads) connected to individual or all circuit components. By way of an appropriate interface, a testing device is connected to these external connections. With the aid of this testing device, the circuit components on the base plate are then tested. In this arrangement, however, it is presumed that the circuit components are digital units in which, in addition to the constructional elements required for normal operation, additional constructional elements are integrated with control connections with which the circuit component for the test can be switched to a pseudo operating condition in which the functionality of all the constructional elements can be determined. Because of the additional constructional elements, a certain proportion of the useful surface at the circuit components becomes lost, the required additional connections reducing the number of connections that are actually useful during operation. By connecting the base plate to the interface of the testing circuit, the latter is occupied for the entire duration of the testing process so that the throughput of tested base plates is small unless the duration of testing is reduced at the expense of the resulting inaccuracies and incompleteness.
Other prior publications have suggested that each circuit component have its own testing circuit permanently built into it. This causes large proportions of area of the circuit components as well as the available external connections of the finished units to be lost. Further, these circuit components have to be tested individually, which is very time consuming. Errors are detected only in the final condition of the circuit component, so that many manufacturing steps required to reach the final condition result in a waste of time.
It is the object of the invention to develop the circuit arrangement for testing circuit components which are formed as integrated circuits so that economic testing is possible.